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<a name="NDS32_002dOps"></a>
<div class="header">
<p>
Previous: <a href="NDS32_002dRegs.html#NDS32_002dRegs" accesskey="p" rel="prev">NDS32-Regs</a>, Up: <a href="NDS32-Syntax.html#NDS32-Syntax" accesskey="u" rel="up">NDS32 Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="Pseudo-Instructions"></a>
<h4 class="subsubsection">9.30.2.3 Pseudo Instructions</h4>
<dl compact="compact">
<dt><code>li rt5,imm32</code></dt>
<dd><p>load 32-bit integer into register rt5.  &lsquo;<samp>sethi rt5,hi20(imm32)</samp>&rsquo; and then
&lsquo;<samp>ori rt5,reg,lo12(imm32)</samp>&rsquo;.
</p>
</dd>
<dt><code>la rt5,var</code></dt>
<dd><p>Load 32-bit address of var into register rt5.  &lsquo;<samp>sethi rt5,hi20(var)</samp>&rsquo; and
then &lsquo;<samp>ori reg,rt5,lo12(var)</samp>&rsquo;
</p>
</dd>
<dt><code>l.[bhw] rt5,var</code></dt>
<dd><p>Load value of var into register rt5.  &lsquo;<samp>sethi $ta,hi20(var)</samp>&rsquo; and then
&lsquo;<samp>l[bhw]i rt5,[$ta+lo12(var)]</samp>&rsquo;
</p>
</dd>
<dt><code>l.[bh]s rt5,var</code></dt>
<dd><p>Load value of var into register rt5.  &lsquo;<samp>sethi $ta,hi20(var)</samp>&rsquo; and then
&lsquo;<samp>l[bh]si rt5,[$ta+lo12(var)]</samp>&rsquo;
</p>
</dd>
<dt><code>l.[bhw]p rt5,var,inc</code></dt>
<dd><p>Load value of var into register rt5 and increment $ta by amount inc.
&lsquo;<samp>la $ta,var</samp>&rsquo; and then &lsquo;<samp>l[bhw]i.bi rt5,[$ta],inc</samp>&rsquo;
</p>
</dd>
<dt><code>l.[bhw]pc rt5,inc</code></dt>
<dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc.
&lsquo;<samp>l[bhw]i.bi rt5,[$ta],inc.</samp>&rsquo;
</p>
</dd>
<dt><code>l.[bh]sp rt5,var,inc</code></dt>
<dd><p>Load value of var into register rt5 and increment $ta by amount inc.
&lsquo;<samp>la $ta,var</samp>&rsquo; and then &lsquo;<samp>l[bh]si.bi rt5,[$ta],inc</samp>&rsquo;
</p>
</dd>
<dt><code>l.[bh]spc rt5,inc</code></dt>
<dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc.
&lsquo;<samp>l[bh]si.bi rt5,[$ta],inc.</samp>&rsquo;
</p>
</dd>
<dt><code>s.[bhw] rt5,var</code></dt>
<dd><p>Store register rt5 to var.
&lsquo;<samp>sethi $ta,hi20(var)</samp>&rsquo; and then &lsquo;<samp>s[bhw]i rt5,[$ta+lo12(var)]</samp>&rsquo;
</p>
</dd>
<dt><code>s.[bhw]p rt5,var,inc</code></dt>
<dd><p>Store register rt5 to var and increment $ta by amount inc.
&lsquo;<samp>la $ta,var</samp>&rsquo; and then &lsquo;<samp>s[bhw]i.bi rt5,[$ta],inc</samp>&rsquo;
</p>
</dd>
<dt><code>s.[bhw]pc rt5,inc</code></dt>
<dd><p>Continue storing register rt5 to var and increment $ta by amount inc.
&lsquo;<samp>s[bhw]i.bi rt5,[$ta],inc.</samp>&rsquo;
</p>
</dd>
<dt><code>not rt5,ra5</code></dt>
<dd><p>Alias of &lsquo;<samp>nor rt5,ra5,ra5</samp>&rsquo;.
</p>
</dd>
<dt><code>neg rt5,ra5</code></dt>
<dd><p>Alias of &lsquo;<samp>subri rt5,ra5,0</samp>&rsquo;.
</p>
</dd>
<dt><code>br rb5</code></dt>
<dd><p>Depending on how it is assembled, it is translated into &lsquo;<samp>r5 rb5</samp>&rsquo;
or &lsquo;<samp>jr rb5</samp>&rsquo;.
</p>
</dd>
<dt><code>b label</code></dt>
<dd><p>Branch to label depending on how it is assembled, it is translated into
&lsquo;<samp>j8 label</samp>&rsquo;, &lsquo;<samp>j label</samp>&rsquo;, or &quot;&lsquo;<samp>la $ta,label</samp>&rsquo; &lsquo;<samp>br $ta</samp>&rsquo;&quot;.
</p>
</dd>
<dt><code>bral rb5</code></dt>
<dd><p>Alias of jral br5 depending on how it is assembled, it is translated
into &lsquo;<samp>jral5 rb5</samp>&rsquo; or &lsquo;<samp>jral rb5</samp>&rsquo;.
</p>
</dd>
<dt><code>bal fname</code></dt>
<dd><p>Alias of jal fname depending on how it is assembled, it is translated into
&lsquo;<samp>jal fname</samp>&rsquo; or &quot;&lsquo;<samp>la $ta,fname</samp>&rsquo; &lsquo;<samp>bral $ta</samp>&rsquo;&quot;.
</p>
</dd>
<dt><code>call fname</code></dt>
<dd><p>Call function fname same as &lsquo;<samp>jal fname</samp>&rsquo;.
</p>
</dd>
<dt><code>move rt5,ra5</code></dt>
<dd><p>For 16-bit, this is &lsquo;<samp>mov55 rt5,ra5</samp>&rsquo;.
For no 16-bit, this is &lsquo;<samp>ori rt5,ra5,0</samp>&rsquo;.
</p>
</dd>
<dt><code>move rt5,var</code></dt>
<dd><p>This is the same as &lsquo;<samp>l.w rt5,var</samp>&rsquo;.
</p>
</dd>
<dt><code>move rt5,imm32</code></dt>
<dd><p>This is the same as &lsquo;<samp>li rt5,imm32</samp>&rsquo;.
</p>
</dd>
<dt><code>pushm ra5,rb5</code></dt>
<dd><p>Push contents of registers from ra5 to rb5 into stack.
</p>
</dd>
<dt><code>push ra5</code></dt>
<dd><p>Push content of register ra5 into stack. (same &lsquo;<samp>pushm ra5,ra5</samp>&rsquo;).
</p>
</dd>
<dt><code>push.d var</code></dt>
<dd><p>Push value of double-word variable var into stack.
</p>
</dd>
<dt><code>push.w var</code></dt>
<dd><p>Push value of word variable var into stack.
</p>
</dd>
<dt><code>push.h var</code></dt>
<dd><p>Push value of half-word variable var into stack.
</p>
</dd>
<dt><code>push.b var</code></dt>
<dd><p>Push value of byte variable var into stack.
</p>
</dd>
<dt><code>pusha var</code></dt>
<dd><p>Push 32-bit address of variable var into stack.
</p>
</dd>
<dt><code>pushi imm32</code></dt>
<dd><p>Push 32-bit immediate value into stack.
</p>
</dd>
<dt><code>popm ra5,rb5</code></dt>
<dd><p>Pop top of stack values into registers ra5 to rb5.
</p>
</dd>
<dt><code>pop rt5</code></dt>
<dd><p>Pop top of stack value into register. (same as &lsquo;<samp>popm rt5,rt5</samp>&rsquo;.)
</p>
</dd>
<dt><code>pop.d var,ra5</code></dt>
<dd><p>Pop value of double-word variable var from stack using register ra5
as 2nd scratch register. (1st is $ta)
</p>
</dd>
<dt><code>pop.w var,ra5</code></dt>
<dd><p>Pop value of word variable var from stack using register ra5.
</p>
</dd>
<dt><code>pop.h var,ra5</code></dt>
<dd><p>Pop value of half-word variable var from stack using register ra5.
</p>
</dd>
<dt><code>pop.b var,ra5</code></dt>
<dd><p>Pop value of byte variable var from stack using register ra5.
</p>
</dd>
</dl>

<hr>
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